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sames sa9203/5 pds039-sa9203/5-001 rev. a 20-08-96 features n six (sa9203) or three (SA9205) 8-bit i/o ports n each bit of one port independently programmable as input or output n five (sa9203) or two (SA9205) remaining ports can be individually configured as input or output. (direction applicable to all 8 pins of each port.) n one 8-bit port programmable as either atched or transparent inputs n supports byte-wide and bit-wide i/o port addressing modes on all ports n readback of all control and port registers n interfaces directly with multiplexed address and data bus microprocessors/ microcontrollers n internal address latch n single +5v power supply n low power cmos n completely static operation n ttl-level compatibility 4491 1/14 6/3 x 8 port expander description the sames sa9203/5 port expander is a cmos device suited to microprocessor based applications requiring input/output port expansion. the device interfaces very simply to any microcontroller/micro- processor with a multiplexed address/data bus structure. the sa9203 includes 8 independently programmable i/o pins for port a and port b to f (5 ports) independently programmable as i/o. it is packaged in a pcb efficient 68 pin plcc package. the SA9205 includes 8 independently programmable i/o pins for port a with port b and port c as indepen- dently programmable i/o, packaged in a cost effective 44 pin plcc package. figure 1: pin connection for sa9203 2 v ss sa9203 8 a 35 0 19 28 pc 1 pc dr-01266 1 4 5 7 pb pb pb pb 2 pb 3 pb 6 pb 27 0 20 21 22 23 24 26 25 pc pc pc pc pc pc 31 33 34 6 7 5 2 3 4 29 30 32 9 stb pa 1 2 3 5 6 4 0 pa pa pa pa pa pa v 7 pa pb 17 11 10 12 13 14 15 16 18 dd cs 876 543 rst wr int ale rd pe 6 50 41 42 pd 6 pd pd pd pd pd pd 40 4 5 0 1 3 2 36 37 38 39 pd pe pe pe pe 5 2 3 4 pe pe 0 1 43 7 46 45 44 47 48 49 63 2 ad 1 666564 67 68 ss 7 6 5 v ad ad ad 4 3 ad ad pf pf pf 3 4 5 pf pf 0 2 1 pf pf 6 pe 7 v dd 53 57 58 56 55 54 59 52 51 pf 7 61 62 60 1 ad 0 ad
sa9203/5 sames 2/14 figure 2: block diagram for sa9203 figure 3: pin connection for SA9205 inter dr-01267 face ad(7:0 con prtb con prta m m int rst wr ale cs rd stb p por f por d por e pe(7: pf(7: pd(7: por a por c por b pc(7: pa(7: pb(7: 2 ad 5 22 0 SA9205 14 pa 0 pa pa pa 18 pa dr-01268 4 15 16 17 3 2 1 pa pa pa pb 20 21 19 5 6 7 ale wr rd int v stb rst cs ad ad nc 6 9 10 11 12 13 dd 7 8 543 7 6 32 pc 1 31 29 30 3 pb pb pb ss v 23 25 24 1 2 pb pb 26 27 28 4 5 pb pb pc 6 7 0 35 36 33 34 37 38 39 ad ad ad ad ss ad 143 44 v 42 41 40 2 3 4 0 1 pc 5 pc pc v pc 3 4 dd 2 pc pc 6 7
sa9203/5 sames 3/14 absolute maximum ratings* (all voltages are with respect to vss) parameter symbol min max unit supply voltage v dd -v ss v ss 7,0 v voltage on any pin v m v ss -0.3 v dd +0.3 v current at any pin i m 100 ma storage temperature t stg -40 +125 c operating temperature t o 0 +70 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other condition above those indicated in the operational sections of this specification, is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. figure 4: block diagram for SA9205 inter- face dr-01269 ad(7:0) con prta con. prtbc m m int rst wr ale cs rd stb p port a port c port b pc(7:0) pa(7:0) pb(7:0)
sa9203/5 sames 4/14 electrical characteristics (all measurements with respect to vss, at 25c, unless otherwise specified) parameters symbol min typ max unit condition supply voltage v dd 4.75 5.0 5.25 v static current i dds 15 50 a vdd = 5.0v (see note1) dynamic current i ddd 20 ma vdd = 5.0v input high voltage v ih 2.0 v vdd = 5.0v input low voltage v il 1.0 v vdd = 5.0v output high voltage v oh 4.5 4.7 v vdd = 5.0v i oh = 5ma output low voltage v ol 0.25 0.5 v vdd = 5.0v i oh = 5ma input leakage current i in <1.0 3.0 a vdd = 5.0v tristate leakage current i tl <1.0 3.0 a vdd = 5.0v note 1 : all inputs tied to vdd or vss with outputs not loaded. measurements made after rst applied.
sa9203/5 sames 5/14 pin type designation description 18,52 vdd +5v supply input 1,35 vss 0v ground reference 61..68 i/o ad0..ad7 3-state address/data lines that interface with the cpu lower 8-bit address/data bus. the 8-bit address is latched into the sa9203 internal address latch on the falling edge of ale. the 8-bit data is respectively written into and read out of the sa9203 on wr and rd signals. 2 n/c not connected. 3 i cs active low input signal used to select the device. 4 i ale this control signal latches the address on the ad0..7 lines on the falling edge of ale. 5 i rd input low on this line enables the data bus buffers. 6 i wr input low on this line causes the data on the address/ data bus to be written to the i/o ports and, control registers. 7 o int if enabled via a.6, this output will be set (active edge polarity programmed by d6 and output polarity programmed via d7 of the port b-f direction control register) after data has been latched into port a. 8 i rst input low on this line resets the chip and all internal registers and all ports to input mode (the register contents after a reset pulse will be described later). 9 i stb input data on port a pins will be latched when stb is active and transparent otherwise (polarity programmed by d5 of the port b-f direction control register) 10..17 i/o pa0..pa7 8 general purpose i/o pins comprising port a. this port supports individual input or latched output configuration of each pin. in addition,each pin of port a selected as an input can be programmed to be latched or transparent. 19..26 i/o pb0..pb7 8 general purpose i/o pins comprising port b. all 8 pins are programmed to be either latched outputs or transparent inputs. 27..34 i/o pc0..pc7 identical to port b 36..43 i/o pd0..pd7 identical to port b 44..51 i/o pe0..pe7 identical to port b 53..60 i/o pf0..pf7 identical to port b pin description for sa9203
sa9203/5 sames 6/14 pin type designation description 2,35 vdd +5v supply input 1,23 vss 0v ground reference 40..44 i/o ad0..ad7 3-state address/data lines that interface with the cpu lower 8-bit address/data bus. the 8-bit address is latched into the sa9203 internal address latch on the falling edge of ale. the 8-bit data is respectively written into and read out of the sa9203 on wr and rd signals. 5 n/c not connected. 6 i cs active low input signal used to select the device. 7 i ale this control signal latches the address on the ad0..7 lines on the falling edge of ale. 8 i rd input low on this line enables the data bus buffers. 9 i wr input low on this line causes the data on the address/ data bus to be written to the i/o ports and, control registers. 10 o int if enabled via a.6, this output will be set (active edge polarity programmed by d6 and output polarity programmed via d7 of the port b-f direction control register) after data has been latched into port a. 11 i rst input low on this line resets the chip and all internal registers and all ports to input mode (the register contents after a reset pulse will be described later). 13 i stb input data on port a pins will be latched when stb is active and transparent otherwise (polarity programmed by d5 of the port b-f direction control register) 14..21 i/o pa0..pa7 8 general purpose i/o pins comprising port a. this port supports individual input or latched output configuration of each pin . in addition,each pin of port a selected as an input can be programmed to be latched or transparent. 22, i/o pb0..pb7 8 general purpose i/o pins comprising port b. all 8 24.30 pins are programmed to be either latched outputs or transparent inputs. 31..39 i/o pc0..pc7 identical to port b pin description for SA9205
sa9203/5 sames 7/14 functional description the sa9203 contains the following: six 8-bit general purpose i/o ports programmable to be either byte or bit addressable. two control registers for configuring the device. these control registers can be read back. an internal address latch for accessing a multiplexed cpu address/data bus. the sa9203 appears to the cpu as a peripheral device occupying 256 bytes of memory space. certain locations in the memory map are occupied by the six i/o ports and two control registers. the sa9203 supports two basic i/o port addressing modes, via; byte-addressing and bit-addressing. any of the six i/o ports can be configured as byte-addressable /or bit- addressable. in bit-addressing, individual bits of any i/o port can be addressed independently. in a bit- addressing cpu read operation, d0 contains valid data while d1..d7 should be ignored. in a bit-addressing cpu write operation, d0 will be written to the addressed output pin while d1..d7 will be ignored. the address memory map is shown in figure 5. the bit-addressing mode applies to both the i/o ports and the control registers. the SA9205 is a three port device with operation is identical to the sa9203. figure 5: address memory map wwwwwwww a7 a6 a5 a4 a3 a2 a1 a0 bm ei cr2 cr1 cr0 bm2 mb1 bm0 bit mode address 0 bit mode address 1 bit mode address 2 control register address 0 control register address 1 control register address 2 0: interupt function disabled 1: interupt function enabled 0: bit mode addressing enabled 1: byte mode addressing enabled
sa9203/5 sames 8/14 figure 6: port a direction control register address. a5 a4 a3 110 figure 7: port b..f direction control register / strobe control register address a5 a4 a3 11 1 figure 8: port addresses a5 a4 a3 port 0 0 0 port a 0 0 1 port b 0 1 0 port c 0 1 1 port d * 1 0 0 port e * 1 0 1 port f * * - n/a for the SA9205 figure 9: port pin addresses (bit mode only). a2 a1 a0 port pin 0 0 0 port a-f.0 0 0 1 port a-f.1 0 1 0 port a-f.2 0 1 1 port a-f.3 1 0 0 port a-f.4 1 0 1 port a-f.5 1 1 0 port a-f.6 1 1 1 port a-f.7 note : port a-c for SA9205 control registers figure 10: port a direction control register r/w r/w r/w r/w r/w r/w r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 pa.7 pa.6 pa.5 pa.4 pa.3 pa.2 pa.1 pa.0 d = 1 port a pin configured as output d = 0 port a pin configured as input.
sa9203/5 sames 9/14 figure 11: port b-f direction control / strobe control register address r/w r/w r/w r/w r/w r/w r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 ip ie sp df* de* dd* dc db 0: port b configured as input 1: port b configured as output 0: port c configured as input 1: port c configured as output 0: port d configured as input 1: port d configured as output 0: port e configured as input 1: port e configured as output 0: port f configured as input 1: port f configured as output 0: port a data latched when stb low and transparent when stb high. 1 - port a data latched when stb high and transparent when stb low. 0 - interupt output (int) set on the rising edge of stb. 1 - interupt output (int) set on the falling edge of stb. 0: interupt output active high 1: interupt output active low * n/a for the SA9205
sa9203/5 sames 10/14 int this active high output (default after reset) operates as follows: when disabled (via a6), int remains reset. on either the rising or trailing edge of stb (programmable via d6 of port b-f direction control register), int is set. int remains set until port a (or any bit of port a if in bit- addressing mode) is read by the microprocessor at which point int is reset, remaining so until the next active edge of stb. (see figure 14 for timing diagram). the output polarity of int is programmed via d7 of the port b- f dirction control register (see figure 11). rst this active low reset signal resets the contents of all registers to zero. sets all ports to input mode and the bi-directional data/address bus to input. a valid rst signal is specified as an active low pulse of 100ns minimum duration. cs the active low cs signal is internally latched by the trailing edge of ale. timing diagrams figure 12: p read waveforms rde t t t rd dr-01270 ll lc t ale cs ad -8/a al t 08 la t ad t address rdf t t rd t cc ld rv t cl t data valid
sa9203/5 sames 11/14 figure 13: p write waveforms figure 14: p strobe/interrupt waveforms dr-01271 ale wr cll t ll t t lc ad -8/a cs 0 address 8 al t la t t cc wd t t rv t wt data valid dw t cl t input data from porta * dependent on sp # dependent on ip dr-01272 int int or stb stb or* pss ss t t t si phs t rdi t
sa9203/5 sames 12/14 figure 16: p read waveforms latched output table 1: ac characteristics for p interface1 - ta = 0c to 70c, vdd = 5v 10% symbol parameter min max units t al address to latch setup time 10 ns t la address hold time after latch 10 ns t lc latch to read/write control 10 ns t rd valid data out delay from read control 50 ns t ld latch to data out valid 50 ns t ad address stable to data out valid 100 ns t ll latch enable width 30 ns t rdf data bus float after read 0 40 ns t cl read/write control to latch enable 10 ns t cll write control to latch enable 50 ns t cc read/write control width 60 ns t dw data in to write setup time 20 ns t wd data in hold time after write 20 ns t rv recovery time between read/write 50 ns t rde data bus enable from read control 10 ns figure 15: i/o port waveforms transparent output data bus * dr 01273 input rd x pr t data valid rp t output dr-01274 data bus * wr x data valid wp t x
sa9203/5 sames 13/14 table 2: a.c. characteristics for i/o ports symbol parameter min max units t pr port input setup time 20 ns t rp port input hold time 0 ns t ss strobe width 100 ns t si strobe to int set 100 ns t rd read to int reset 100 ns t pss port setup time to strobe 50 ns t phs port hold time after strobe 120 ns t wp write to port output 80 ns note 1: timing parameters are preliminary and subject to change.
sa9203/5 sames 14/14 south african micro-electronic systems (pty) ltd p o box 15888, 33 eland street, lynn east, koedoespoort industrial area, 0039 pretoria, republic of south africa, republic of south africa tel: 012 333-6021 tel: int +27 12 333-6021 fax: 012 333-8071 fax: int +27 12 333-8071 disclaimer: the information contained in this document is confidential and proprietary to south african micro- electronic systems (pty) ltd ("sames) and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of sames. the information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. sames does not undertake to inform any recipient of this document of any changes in the information contained herein, and sames expressly reserves the right to make changes in such information, without notification,even if such changes would render information contained herein inaccurate or incomplete. sames makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer.

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